Welcome to AVL-RAL's Documentation
=========================================

What is AVL?
------------

**AVL** is the Apheleia Verification Library.

For full details see `AVL Documentation <https://avl-core.readthedocs.io/en/latest/>`_.

What is AXI-RAL?
-------------------

**AXI-RAL** is the Register Abstraction Layer for the AVL library.

Why Use AVL-RAL?
----------------

AVL-RAL is a library designed to provided a simple API for accessing registers and fields within an AVL test-bench. \

AVL-RAL is quick and easy to integrate into any test-bench provided the registers are defined in `systemrdl <https://github.com/SystemRDL>`_ \
format or `IPXACT <https://accellera.org/images/downloads/standards/ip-xact/IPXACT-2022_user_guide.pdf>`_ XML format.

AVL-RAL provides both:

- Front-door access. Via read / write callbacks.

- Back-door access. Via peek / poke methods (after assigning a HDL path to the underlying state).

Unlike UVM-RAL, AVL-RAL makes no attempt to model the wide range of user defined register definitions. These often involve difficult hardware interactions \
resulting in the user creating too many hooks into the RTL for the test-bench to remain simple and HDL independent.

Instead, AVL-RAL implements read and write callbacks for registers, but fields update by a register read-modify-write (as would be used by Software).